64Kx16 LP SRAM EM6164K600V Series
GENERAL DESCRIPTION
The EM6164K600V is a 1,048,576-bit low power CMOS static random access memory organized as
65,536 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology.
Its standby current is stable within the range of operating temperature.
The EM6164K600V is well designed for low power application, and particularly well suited for battery
back-up nonvolatile memory application.
The EM6164K600V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
FEATURES
Fast access time: 45/55/70ns
Low power consumption:
Operating current:
23/20/18mA (TYP.)
Standby current: -L/-LL version
10/1µA (TYP.)
Single 2.7V ~ 3.6V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control :
LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage: 1.5V (MIN.)
Package:
44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A15
DECODER
64Kx16
MEMORY
ARRAY
DQ0-DQ7
Lower Byte
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
UB#
I/O DATA
CURCUIT
COLUMN I/O
CONTROL
CIRCUIT
PIN DESCRIPTION
SYMBOL
A0 - A15
DQ0 – DQ15
CE#
WE#
OE#
LB#
UB#
Vcc
Vss
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
Power Supply
Ground
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DCC-SR-041002-A
64Kx16 LP SRAM EM6164K600V Series
PIN CONFIGURATION
TSOP-II
A4
A3
A2
A1
A0
CE#
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE#
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE#
UB#
LB#
DQ15
DQ14
DQ13
DQ12
Vss
Vcc
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
TFBGA
A
B
C
D
E
F
G
H
LB#
DQ8
DQ9
Vss
Vcc
DQ14
DQ15
NC
1
OE#
UB#
DQ10
DQ11
DQ12
DQ13
NC
A8
2
A0
A3
A5
NC
NC
A14
A12
A9
3
A1
A4
A6
A7
NC
A15
A13
A10
4
A2
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
5
NC
DQ0
DQ2
Vcc
Vss
DQ6
DQ7
NC
6
2
DCC-SR-041002-A
64Kx16 LP SRAM EM6164K600V Series
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
SOLDER
RATING
-0.5 to 4.6
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
260
°C
W
mA
°C
°C
UNIT
V
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
TRUTH TABLE
MODE
Standby
Output
Disable
Read
Write
CE#
H
X
L
L
L
L
L
L
L
L
OE#
X
X
H
H
L
L
L
X
X
X
WE#
X
X
H
H
H
H
H
L
L
L
LB#
X
H
L
X
L
H
L
L
H
L
UB#
X
H
X
L
H
L
L
H
L
L
I/O OPERATION
DQ0-DQ7
DQ8-DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
OUT
High-Z
High-Z
D
OUT
D
OUT
D
OUT
D
IN
High-Z
High-Z
D
IN
D
IN
D
IN
SUPPLY CURRENT
I
SB
,I
SB1
I
CC
,I
CC1
I
CC
,I
CC1
I
CC
,I
CC1
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage
Current
Output Leakage
Current
Output High
Voltage
Output Low
Voltage
Average Operating
Power supply
Current
SYMBOL
Vcc
V
IH
*1
V
IL
*2
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC1
Standby Power
I
SB
TEST CONDITION
MIN.
2.7
2.0
-0.2
-1
-1
2.2
-
-45
-55
-70
-
-
-
-
-
TYP.
*5
3.0
-
-
-
-
2.7
-
23
20
18
4
0.3
MAX.
3.6
Vcc+
0.3
0.6
+1
1
-
0.4
40
35
30
5
0.5
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
Vcc
≧
V
IN
≧
Vss
V
CC
≧
V
OUT
≧
V
SS
,
Output Disabled
I
OH
= -1mA
I
OL
= 2mA
Cycle time = Min.
CE# = V
IL
, I
I/O
= 0mA
Cycle time = 1µs
CE#
≦
0.2V and I
I/O
= 0mA
other pins at 0.2V or V
CC
-0.2V
CE# = V
IH
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DCC-SR-041002-A
64Kx16 LP SRAM EM6164K600V Series
Supply Current
I
SB1
CE# V
≧
V
CC
- 0.2V
-L
-LL
-
20
1
80
10
µA
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10µA for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C
CAPACITANCE
(T
A
= 25°C , f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX.
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
SYM.
t
RC
t
AA
t
ACE
t
OE
t
CLZ
*
t
OLZ
*
t
CHZ
*
t
OHZ
*
t
OH
t
BA
t
BHZ
*
t
BLZ
*
-45
MIN. MAX.
45
-
-
45
-
45
-
25
10
-
5
-
-
15
-
15
10
-
-
45
-
20
10
-
-55
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
-
55
-
25
10
-
70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
-
70
-
30
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM.
t
WC
t
AW
t
CW
t
AS
t
WP
t
wr
t
DW
t
DH
t
OW
*
t
WHZ
*
t
BW
-45
MIN. MAX.
45
-
40
-
40
-
0
-
35
-
0
-
20
-
0
-
5
-
-
15
35
-
-55
MIN. MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
20
45
-
70
MIN. MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
25
60
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
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DCC-SR-041002-A
64Kx16 LP SRAM EM6164K600V Series
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled) (1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous Data Valid
Data Valid
READ CYCLE 2
(CE# and OE# Controlled) (1,3,4,5)
t
RC
Address
t
AA
CE#
OE#
t
ACE
t
OH
t
OE
t
OLZ
t
CLZ
t
OHZ
t
CHZ
Valid Data
t
BLZ
t
BA
t
BHZ
Dout
High-Z
LB#, UB#
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
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DCC-SR-041002-A
